Asian Science Citation Index is committed to provide an authoritative, trusted and significant information by the coverage of the most important and influential journals to meet the needs of the global scientific community.  
ASCI Database
308-Lasani Town,
Sargodha Road,
Faisalabad, Pakistan
Fax: +92-41-8815544
Contact Via Web
Suggest a Journal
Articles by Har Narayan Upadhyay
Total Records ( 8 ) for Har Narayan Upadhyay
  V. Elamaran , Har Narayan Upadhyay , K. Narasimhan and J. Jezebel Priestley
  Image enhancement plays a vital role in the field of digital image processing since the noise is added very often with the original image. Spatial filtering techniques like low pass, high pass, band pass and notch with the help of convolution mask are often used to enhance the image with reduced noise. Recently, morphological algorithms play a major role in the area of filtering noise, boundary detection, shape detection, image manipulation, etc. Especially by applying dilation, erosion, opening and closing to the image appropriately, the quality of the image can be further enhanced. In this study, morphological algorithms are being applied to remove the salt and pepper noise from the input image. Erosion followed by dilation and dilation followed by erosion are the main methods to remove this kind of impulsive noise. MATLAB software is used to apply these opening and closing methods to enhance the quality of the image with difference structuring elements. Simulation results are obtained and the comparison is done with the performance metrics like Peak Signal-to-Noise Ratio (PSNR), Mean Absolute Error (MAE), Normalized Correlation Coefficient (NCC) and Image Enhancement Factor (IEF) with different structuring elements.
  V. Elamaran and Har Narayan Upadhyay
  Rapid increase in technology for faster and smarter innovations that smoothens the needs of humans resulting in use of super tech gadgets, which use memory, such as, RAM. To meet the increasing demands, the size is getting reduced and the need to save power arises which reduces the equipment for cooling processes and maintenance. The SRAM cells with lower power dissipation and proper read and write stability is required. This study deals with the design of SRAM cells with low power dissipation in comparison with the conventional SRAM cell design. The SRAM cell design ranges from 3-14T depending on the importance of the application. Here we choose the 6T SRAM cell. The elementary structure uses pass transistor and CMOS, while the proposed SRAM consists of Transmission gates, CMOS, Pseudo-NMOS. This proposed model is compared with two other models of varied 6T SRAM cell. This study also exemplify with the new Triple Modular Redundancy (TMR) techniques with SRAM cell architecture and the layout area with power dissipation results are compared with the existing voting mechanism in 50, 70 90 and 120 nm foundry fabrication process technologies. It is apparent that the proposed voting circuit produces less area at the cost of power dissipation.
  V. Elamaran and Har Narayan Upadhyay
  Since the performance of portable electronic products increases continuously with demand, there is a need for low power digital VLSI design. Due to limited backup time of batteries, the operating time of portable electronic products is highly restricted. So, the designers now concentrate on low power rather than the speed of the device or system. We implement a 4 bit barrel shifter using different flavors like conventional CMOS logic, pass transistor logic and transmission gate logic styles. Electronic Computer Aided Design (CAD) tools like Microwind and a DSCH are used in our simulations by which the comparison of power in each style is provided. Microwind is used a layout editor and DSCH (Digital Schematic) is used as a schematic editor. Results show that the pass transistor logic consumes less power with minimum area and good performance. We used BSIM4 MOSFET model in 0.12 μm for experimental results. To improve the reliability of the circuits, fault tolerant voter circuits are implemented. The results are compared with the existing approaches and the proposed methods.
  Sundararaman Rajagopalan , K. Pravallika , R. Radha , Har Narayan Upadhyay , J.B.B. Rayappan and Rengarajan Amirtharajan
  The inventions and innovations in the multimedia communication have revolutionized the infotainment world. With the advancements in multimedia , there is a growing demand to use the image, audio, video and text ingredients for information protection. In the field of steganography, the cover to carry over the secret information has been an image in many of the reported works due to high payload carrying capacity. However audio steganography on hardware platform provides the user an option to use multicarrier steganography on common chip. Here we propose a method of steganography which has been implemented on Cyclone II FPGA EP2C20F484C7 which houses an architecture with LSB substitution of Huffman encoded secret message on select parts of digitized audio signal. The experimental results show that a SNR of 127.7 dB has been obtained for 100 bits payload with embedding process done on every 2000th memory location of 16-bit digitized audio signal stored in External SRAM.
  Sundararaman Rajagopalan , Har Narayan Upadhyay , Swetha Varadarajan , J.B.B. Rayappan and Rengarajan Amirtharajan
  The growing demand to protect the confidential messages and documents paved way for the invent of information security techniques. Whatever, be the strength of security algorithms and standards, an equal amount or greater than that attempt is made to crack the information which employs an algorithm to make it invisible to anonymous. New techniques and algorithms will help a lot for strengthening the security of our information systems. Steganography is basically a science turned art to hide the payload with the help of a carrier. We propose a spatial domain image steganography technique which uses two aspects for information hiding-one being the pixel nibble difference and the other in the form of block rotation decided by a variable P’. This technique adds a technique to the group of information hiding techniques where block rotation can be decided by various parameters concerned with the carrier which may be audio, video or text.
  Sundararaman Rajagopalan , Pakalapati J.S. Prabhakar , Mucherla Sudheer Kumar , N.V.M. Nikhil , Har Narayan Upadhyay , J.B.B. Rayappan and Rengarajan Amirtharajan
  Information hiding as a field is extremely fast developing and one of the very few fields that derive its power from its inherent need for sophistication and complexity in its algorithms. Out of the ever growing list of information hiding methods, steganography has emerged as the front runner because of clandestine nature. Image steganography is the heart of steganography because of wide availability of images in local media, variable capacity and its ability to cloak the very existence of secret data in it. There are innumerable software methods available for steganography but there is a dearth of hardware implementations to serve this purpose. In this study, we have devised a FPGA implementation that randomises the volume of data embedded in each pixel, according to the same MSBs. This implementation also contains a novel method to check the integrity of the embedded data by providing a mechanism by which we can weed out any modifications in the secret data, to an extent that it can even pinpoint the exact pixel in which the change has occurred. This algorithm has been implemented on EP2C35F672C6 FPGA. The synthesis report and Timing analysis have also been discussed in this study.
  Sundararaman Rajagopalan , Yamini Ravishankar , Har Narayan Upadhyay , J.B.B. Rayappan and Rengarajan Amirtharajan
  Steganography, a protected envelope for information systems is reaching new horizons at software as well as hardware level. Due to the number of benefits that result in using reconfigurable hardware like FPGA for stego system development, some attention is needed in performing the stego memory testing. While Self test methodologies adopted for memories require attention due to the extensive memory requirements, testing the secret carrier stego memory modules occupies the center stage due to its higher importance of data protection. Normally block RAMs inside FPGA can store the cover and stego images. With the hardware pseudorandom pattern generators, the memory testing can be done effectively. In this regard, the present work focuses on the implementation and analysis of various combined multiple LFSR based pseudorandom sequence generation schemes for Stego Memory self testing on Cyclone II EP2C20F484C7 FPGA. Analysis of the different schemes for their suitability to stego memory arena is an important objective of this work and also sequence distribution analysis has been carried out to verify the distribution of pseudorandom sequences for N clock cycles. The synthesis reports for all the four cases undertaken in this work have also been reported.
  M. Maheswaran , M. Nambirajan , Uppari Chaitanya Chandra Yadav and Har Narayan Upadhyay
  Micro Electromechanical Systems (MEMS) actuators experience pull-in instability in their actuation range. MEMS actuating elements are thin parallel plate capacitor electrodes separated with air gap. The electrodes are fabricated from silicon as substrate layer and gold /aluminum layer as functional layer for reflecting laser beam in optical switching application. When the top electrode is attracted towards bottom electrode, as it crosses one third distance of the gap between the electrodes, it undergoes pull-in/snap-down with bottom electrode. This condition severely limits the device operating range. These devices are operated either analog or digital mode for positioning of the top electrode. The plate electrodes actuated in tilting mode or bending mode and they are typically torsional structures or fixed-fixed structures. This paper provides theoretical pull-in analysis for the static behavior of a optical switch model. It is derived from analytical modeling of the parallel plate type with fixed-fixed structural end conditions. The effect of dielectric layer thickness is taken into account for predicting the pull-in voltage. During the piston mode actuation cycle, when the threshold (pull-in) voltage is reached, the switch is in the bent or ON state due to electrostatic repulsion/attraction and for the no voltage condition it is in the parallel or OFF state. The pull-in hysteresis behavior of the multilayered micro-actuator bending beam model is analyzed for the variation in thickness of dielectric material. In this paper, the critical role of different dielectric layer materials in bringing down the static pull-in voltage is discussed.
Copyright   |   Desclaimer   |    Privacy Policy   |   Browsers   |   Accessibility