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A new chip design paradigm called Network-on-Chip (NoC) offers
a promising architectural choice for future System-on-Chip (SoC). Communication
latency and power efficiency are the most important concerns in NoC architecture
design. Triple-based Hierarchical Interconnection Network (THIN) was proposed
that aims to decrease the node degree, reduce the links and shorten the diameter.
In this study, the zero-load latency and energy consumption are thoroughly studied
and compared with 2-D mesh. The compare results show that THIN is a better candidate
for constructing the NoC than 2-D mesh, when there are not too many nodes.
