Search. Read. Cite.

Easy to search. Easy to read. Easy to cite with credible sources.

Journal of Engineering and Applied Sciences

Year: 2018  |  Volume: 13  |  Issue: 7  |  Page No.: 1596 - 1600

Profiling Based Functional Verification on a Heterogeneous Architecture

S. Karthik and S. Saravana Kuma


This study research involves analyze and explore the study of the current state-of-the-art in parallel logic simulation including simultaneous simulation techniques. Functional verification, a tortuous and tedious task, refers to the verification of any logic design according to the specifications. It’s basically a cumbersome process due to the presence of an enormous number of test cases even for a simple logic design. Logic simulation is used to predict the behavior of digital circuits where the system components can vary from transistor level through the gate level to the behavioral level. Due to increased complexity, large designs, the time taken to test will also be long. To overcome this problem, parallel simulation was employed. Simulation based verification due to its ease in performing is widely used. As the name suggests it allows verifying the performance of various operations simultaneously, there by reducing the time to a considerable extent. So, this method is restored to achieve our goal. To verify our design, we chose a hardware platform named Zybo board (Zynq Z-7010-heterogeneous architecture). As the name suggests, it comprises of FPGA and a 650 MHz cortex-A9 ARM processor which expedites the testing process. We use Vivado tool for profiling, a process which helps one to know which portion of the function takes more time compared to other during the simulation. The portion which takes large time for simulation is port mapped to the FPGA while the rest is assigned to the processor.