Asian Science
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Abstract: Steganography, a protected envelope for information systems
is reaching new horizons at software as well as hardware level. Due to the number
of benefits that result in using reconfigurable hardware like FPGA for stego
system development, some attention is needed in performing the stego memory
testing. While Self test methodologies adopted for memories require attention
due to the extensive memory requirements, testing the secret carrier stego memory
modules occupies the center stage due to its higher importance of data protection.
Normally block RAMs inside FPGA can store the cover and stego images. With the
hardware pseudorandom pattern generators, the memory testing can be done effectively.
In this regard, the present work focuses on the implementation and analysis
of various combined multiple LFSR based pseudorandom sequence generation schemes
for Stego Memory self testing on Cyclone II EP2C20F484C7 FPGA. Analysis of the
different schemes for their suitability to stego memory arena is an important
objective of this work and also sequence distribution analysis has been carried
out to verify the distribution of pseudorandom sequences for N clock cycles.
The synthesis reports for all the four cases undertaken in this work have also
been reported.