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Information Technology Journal
Year: 2013  |  Volume: 12  |  Issue: 19  |  Page No.: 4831 - 4837

Low Voltage Flip-flop Standard Cells with Optimum Energy Delay Product

Yang Dan, Geng Ye-Liang and Hu Jian-Ping    

Abstract: This study presents transmission gate flip-flop standard cells with channel length and dual-threshold techniques and their low-voltage operating. The proposed transmission gate flip-flops have the same structure with the basic master-slave transmission gate one using multiplexers, but the different place is the feedback path (non-critical path). In the non-critical path, the dual-channel length flip-flop uses high threshold devices while the dual-threshold flip-flop uses gate-length modulation device. Three flip-flop standard cells are investigated from 0.5 to 1.2 V in term of Energy Delay Product (EDP) with HSPICE at a SMIC 130 nm technology. The dual-threshold flip-flop standard cell achieves considerable leakage reductions and gate-length biasing flip-flop standard cell achieves the lowest total energy consumption in all the cells. The results demonstrate that scaling supply voltage using dual-threshold CMOS (low threshold and ultra high threshold) and gate-length biasing are advantageous, especially in low voltage regions (800-900 mv) which yield the best EDP.

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