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Information Technology Journal
  Year: 2012 | Volume: 11 | Issue: 10 | Page No.: 1442-1448
DOI: 10.3923/itj.2012.1442.1448
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Fault Tolerance Structure of Radix 2 Signed Digital Adders

Fei Gu, Chunqing Ling, Jishun Kuang and Yingbo Zhou

In this study, structure of fault tolerance adder based on Radix 2 Signed Digital (SD) representation is proposed. The “carry-free” property of the SD adder that faults impact limited to a few digits can be used to fault detection which is based on parity checking assumed single fault set. Using an encoding scheme to get the parity value of digits involved in computing, this parity values can be exploited to check the circuit. An error information register is set to store the checking results and the bits of the register indicate the corresponding units faulty or not. According to the fault type, recomputation or reconfiguration is used to error correction. The hardware overhead appending Fault-Tolerant is about 120% and the maximum combinational path delay of the proposed adder is constant with the increase of operands.
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  •    Improving Fault Tolerance in Ad-Hoc Networks by Using Residue Number System
  •    Algorithm Based Fault Tolerant and Check Pointing for High Performance Computing Systems
  •    A New Moduli Set for Residue Number System in Ternary Valued Logic
  •    Overview of Radiation Hardening Techniques for IC Design
How to cite this article:

Fei Gu, Chunqing Ling, Jishun Kuang and Yingbo Zhou, 2012. Fault Tolerance Structure of Radix 2 Signed Digital Adders. Information Technology Journal, 11: 1442-1448.

DOI: 10.3923/itj.2012.1442.1448






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