Abstract: Background: Pseudo random number generation is an algorithm for generating a stream of numbers as having the appearance of randomness. Random numbers are essential for many applications, including simulations, cryptography and random sampling. In this study, a model of Linear Feedback Shift Register is implemented in Verilog language using Xilinx software. The simulation results demonstrate that it is possible to generate a perfect random sequence. Materials and Methods: Practically, Verilog language is used in order to implement the LFSR and generate a random sequence. Verilog has a random number generator within it but it is permitted to only test benches. In Verilog, some modules will be written such as for flip-flops and multiplexer. In this study, a module naming LFSR is created using different parameters including clock, reset, load, input/seed, etc. Results: Simulation results show the outputs of the LFSR in the software. Xilinx ISE design suite system for the simulation of the Verilog code of the LFSR is used. The sequences are generated from the operations performed by Mux and flip-flop and the feedback too. Conclusion: The LFSR model is implemented in Verilog language using Xilinx software considering suitable time factor, inputs and clock signals. A perfect random sequences and synthesis of implemented model are generated.