Abstract: A new high-speed low-power multiplier has been presented in nanotechnology. Implementing multiplication algorithms in nanotechnology has a major effect in performance of arithmetic processors. A new design for the use of the number system {0, 1, 2, 3}, with a particular three bit coding of digits, is evaluated and some improvements are obtained, including the possibility of using a two bit coding, with a considerable reduction in the wiring of the multiplier structure. Non-regularities in the construction of conventional Wallace tree multipliers consequence in a large quantity of dissipated area when implemented in VLSI. A novel Wallace tree structure is proposed. An evaluation between the critical path and wiring overhead between the conventional and the modified Wallace tree is presented. A fast adder has been implemented. The proposed adder is based on carry chain schemes. A Wallace tree multiplier is designed and simulated in a 70 nm process. We used HSPICE and Synopsys for simulations. The latency has decreased by almost 18% and power consumption decreased by 16%. Our design reduced transistor count by 12%.