Abstract: This study deals with the design of a voltage controlled oscillator designed to be part of a Phase Locked-Loop (PLL), which implements the frequency synthesizer of a Low-IF transceiver. The transceiver operates in the European 433-MHZ ISM band. We focus on low-cost, low-voltage (1... 1.5V) battery operated systems to be used in portable applications (medical care, surveillance systems...). Therefore we want the analog cells to be fully integrated in a single chip solution. In the design of the VCO we developed a Top-Down strategy, starting from high-level specifications such as consumption, operating frequency and phase noise and subsequently deriving transistor sizes and bias. This present study will begin with a look at the basic delay cell operation, including the replica bias circuit used to establish the output swing. Performance as a function of process technology will be considered. The conclusions from this Top-Down methodology will be applied to the design of ring-oscillator inverter delay cells in a 0.35 μm CMOS process. The complete design sequence for the delay cells will be described and transistor sizes determined.