Abstract: Full adders are important components in applications such as Digital Signal Processors (DSP) architectures and microprocessors. Demands for the low power VLSI have been pushing the development of aggressive design methodologies to reduce the power consumption drastically. To meet the growing demand, The present study propose a new low power adder cell by sacrificing the MOS Transistor count that reduces the serious threshold loss problem, considerably increases the speed and decreases the power when compared to the Static Energy Recovery Full (SERF) adder. So a new improved 14T CMOS l-bit full adder cell is presented in the present study. Results show 50% improvement in threshold loss problem, 48% improvement in speed and considerable power consumption over the SERF adder and other different types of adders with comparable performance.