Abstract: This study presents a design of a highly reliable shift register based on TSMC 0.18 μm process which can efficiently fight against the Single Event Upset (SEU). A bilateral Power on Reset (POR) block, together with bit-line segregation and tri-mode redundancy technologies are applied in this design to comprehensively enhance the SEU hardening performance at both system level and circuit level. Assisted by the theory of transient circuit analysis, the shift register’s SEU hardening performance is achieved from the aspects of both schematic and layout. A current pulse which is used to emulate the SEU effect, is injected in the circuit for verification. The result of simulation shows great improvement of the SEU tolerance. With its high reliability and radiation tolerance, the present shift register can be applied to CMOS chip designs in the field of aerospace.