Abstract: With the growing uses of portable computers, energy-efficient designs have become more and more important for computer hardware. This study presents new low leakage power flip-flops with power-gating scheme for ultra-low power systems. The proposed flip-flops are realized based on CMOS ratioed latches with the master-slave structure. Dual-threshold CMOS (DTCMOS) and channel length biasing techniques are used for the flip-flops with power-gating scheme to reduce leakage power dissipations. All circuits are verified with HSPICE simulations by using the BSIM4 predictive models at a 45 nm CMOS process. The results showed that the proposed low leakage ratioed flip-flop realized with the integrated leakage reduction techniques achieves large leakage savings compared with the transmission-gate flip-flop.