Abstract: The most important issue to consider when designing a network system is to choose a technology which is both flexible and fast enough to support the present and future protocols and the high throughput requirements respectively. For this a reconfigurable router is a flexible solution that includes the best features of both hardware and software processing by means of Field Programmable Gate Array (FPGA) technology. Hence in this paper a hardware implementation of TORA protocol using an FPGA is presented. We discuss the proposed architecture of the hardware based TORA router and present the method of implementation in hardware and its Simulation and Synthesis reports are obtained using VHDL. These reports show that the Device summary and Timing analysis, having process cycle of minimum period with 29.27 ns.