Abstract: In this study, we develop a reconfigurable rapid prototyping system with PCI as interface. Reconfigurable processing unit uses I/O coupling way with general propose processor to work in coordination and to accelerate the execution of the specific task. Use four FPGA chip in order to offer the hardware design environment under multi-FPGA structures systematically at the same time. This system except that the intact hardware is designed and implemented, but also include the setting-up of the driver with offer the application program interface which access the hardware. In order to prove that systematic function of rapid prototyping board is correct, design one IP Core to apply to this system. We implement an Advanced Encryption Standard (AES) hardware circuit for this goal. The focal point designed lies in making optimization to resources of FPGA and AES suitability in reconfigurable computing with multi-FPGA system.