Abstract: This study presents an implementation of a Distributed Arithmetic (DA) based reconfigurable Finite Impulse Response (FIR) filter whose filter coefficient dynamically change during runtime. This DA based structure replaces all required multiplication and addition by a Look Up Table (LUT) and shift accumulator. The dual port dynamic RAM (DRAM) used in this work is to reduce the total size of LUT by half. The scheme which are using in shift accumulator doubles the throughput, since two inner products are computed concurrently. Systolic system which consists of an array of processing element in a pipeline structure is used for application such as image processing and signal processing. The proposed work uses mainly a DA based systolic architecture which yields faster output compared to the multiplier-accumulator based design because it stores the pre computed partial result in the memory and used it in computation. The entire architecture is implemented in FPGA from ALTERA family. The proposed architecture consumes 70 nW thermal power in which core static and I/O thermal power dissipations are 47.36 and 22.64 nW, respectively. Another main advantage over DRAM is high data rate, wide data bus size and maximum throughput.