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Asian Journal of Applied Sciences

Year: 2011 | Volume: 4 | Issue: 6 | Page No.: 657-662
DOI: 10.3923/ajaps.2011.657.662
Minimization of Power Dissipation in 16 Bit Processor using Low Power Tecniques
N. Siva Sankara Reddy

Abstract: The need for low power and high efficiency electronics is felt more and more with the proliferation of complex mobile gadgets into our daily use. This paper describes about implementation of low power techniques to different designs using VERILOG HDL (Hardware Description Language) through simulation and synthesis and finally implement some of the low power techniques in the design of 16 bit CPU. The power reports after synthesis indicate that there is about 29% of power saving in the 16 bit processor when these low power techniques are applied.

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How to cite this article
N. Siva Sankara Reddy , 2011. Minimization of Power Dissipation in 16 Bit Processor using Low Power Tecniques. Asian Journal of Applied Sciences, 4: 657-662.

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