Abstract:
In this study, an adaptive biasing CMOS operational amplifier is presented which operates at 3 V power supply and simulated at 180 and 90 nm technologies. The adaptive biasing current circuit controls the input voltages and supplies the amplifier with biasing current in order to achieving stability and optimum power consumption at higher speed. The circuit is simulated in Hspice software environment and the performance results demonstrate that the amplifier with the ABCC can operate with low power and achieve high speed of 0.012 V/us at the time rise and 0.011 V/us at fall time when the input pulse frequency and the amplitude are 1 kHz and 1.3 V peak to peak, respectively. The gain and phase margin are 35 dB and 62° at 90 nm technology, respectively.
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