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Journal of Applied Sciences
  Year: 2014 | Volume: 14 | Issue: 14 | Page No.: 1623-1627
DOI: 10.3923/jas.2014.1623.1627
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A Novel Low Power Adder-Subtractor using Efficient XOR Gates

V. Elamaran, G. Rajkumar, S. Singh Rajpurohit and R. Anooj Krishnan

VLSI system and design trend is moving away from speed constraint to power due to the rapid technology evolution growth in the portable consumer electronics market. The operational time of consumer electronic products are highly limited due to limited backup time of batteries. A novel adder-subtractor using XOR gates which are in turn designed with less number of transistors is implemented. Modification of XOR gate portion in a adder-subtractor using minimum number of transistors is the key idea for the design. In future, a study of modification of the entire circuitry involved in the design will be implemented. A comparison of the results with traditional adder-subtractor using conventional CMOS approach using Electronic Design Automation (EDA) tools like DSCH (Digital Schematic) and Microwind layout tools using BSIM4 MOSFET model in 0.12 μm technology is obtained. Results show that all the three approaches are better than a conventional approach by comparing power, speed and layout area.
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How to cite this article:

V. Elamaran, G. Rajkumar, S. Singh Rajpurohit and R. Anooj Krishnan, 2014. A Novel Low Power Adder-Subtractor using Efficient XOR Gates. Journal of Applied Sciences, 14: 1623-1627.

DOI: 10.3923/jas.2014.1623.1627






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