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Journal of Applied Sciences
  Year: 2013 | Volume: 13 | Issue: 3 | Page No.: 385-392
DOI: 10.3923/jas.2013.385.392
 
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FPGA Implementation of Low Power Digital QPSK Modulator Using Verilog HDL

Asraf Mohamed Moubark, Mohd Alauddin Mohd Ali, Hilmi Sanusi and Sawal Md. Ali

Abstract:
Quadratute Phase Shift Keying (QPSK) is a modulation scheme commonly used in wireless communication system due to its ability to transmit twice the data rate for a given bandwidth. Even though the QPSK modulator consumes less power in a present devices but for a system such as satellite and mobile devices where their operations are power limited, this is an issue that needs attention. The objective of this study is to develop an implementable QPSK modulator that uses less power for operation. The proposed technique uses data stored inside a memory block to produce a symbol according to the input data. On the contrary, the conventional QPSK demodulation process requires a Direct Digital Synthesizer (DDS) to produce sinusoidal waveform and mixers to produce a symbol according to the input data. The proposed modulator successfully modeled with verilog Hardware Description Language (HDL), simulated with Xilinx Integrated Software Environment (ISE) version 12.4 software and implemented on Spartan 3E board. At the same time a QPSK demodulator has been developed using MATLAB tool in order to verify the functionality of the modulator. The measured performances of the modulator show the proposed architecture consumes significantly less 32 mw in total from the conventional architecture. The novelty of this work is that the researchers have focused on new methodology on reducing the modulator operational power. As a conclusion, the proposed architecture is not only able to operate as conventional QPSK modulator but at the same time significantly consumed less operation power.
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How to cite this article:

Asraf Mohamed Moubark, Mohd Alauddin Mohd Ali, Hilmi Sanusi and Sawal Md. Ali, 2013. FPGA Implementation of Low Power Digital QPSK Modulator Using Verilog HDL. Journal of Applied Sciences, 13: 385-392.

DOI: 10.3923/jas.2013.385.392

URL: https://scialert.net/abstract/?doi=jas.2013.385.392

COMMENTS
06 October, 2013
anitha:
I read the paper, I need a help for DDS to generate sine & cosine i am doing the project, So i need to generate sine and cosine what you implemented in your paper. I need your guideline to write verilog code for dds to generate sine and cosine.
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