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Journal of Applied Sciences
  Year: 2011 | Volume: 11 | Issue: 5 | Page No.: 832-839
DOI: 10.3923/jas.2011.832.839
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Systematic Minimization Technique for Majority-Majority Digital Combinational Circuits

Hanan Mahmoud

In CMOS (Complementary Metal Oxide Semiconductor) technology AND-OR combination logic is used because of the ease of its minimization using different well-known techniques such as K-Map. On the other hand, majority gate-based logic is not handled well in standard CMOS technologies, primarily because of the hardware inefficiencies in creating majority gates. As a result no optimization techniques of circuits based on majority gates were established. Promising technologies particularly, Quantum-dot Cellular Automata (QCA) use majority gate as a primary logic primitive instead of the AND-OR combination gates. We report a perceptive systematic minimization technique for reduction of 3-variable, 4-variables and 5-variables Boolean functions into a simplified majority of majority gate representation. The main role of this work is the general and systematic way the new approach can be applied. All attempts in the literature were complex and lacked the extended systematic approach that we are offering. The design of several logical functions will be presented using the new technique. Simulation of these functions are done using QCA designer showing area reduction achievements.
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How to cite this article:

Hanan Mahmoud , 2011. Systematic Minimization Technique for Majority-Majority Digital Combinational Circuits. Journal of Applied Sciences, 11: 832-839.

DOI: 10.3923/jas.2011.832.839






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