P. Swaminathan
School of Computing, SASTRA University, Thanjavur, India
PDF Fulltext XML References Citation
How to cite this article
P. Swaminathan, 2012. Verification and Validation Methodology for Safety Critical Embedded Systems. Journal of Artificial Intelligence, 5: 214-220.
DOI: 10.3923/jai.2012.214.220
URL: https://scialert.net/abstract/?doi=jai.2012.214.220
DOI: 10.3923/jai.2012.214.220
URL: https://scialert.net/abstract/?doi=jai.2012.214.220