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Information Technology Journal
  Year: 2009 | Volume: 8 | Issue: 7 | Page No.: 965-970
DOI: 10.3923/itj.2009.965.970
 
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A Review of Hardware Transactional Memory in Multicore Processors

X. Wang, Zhenzhou Ji, Chen Fu and Mingzeng Hu

Abstract:
In this study, we give a review of the current Hardware Transactional Memory (HTM) systems for Multicore processors. Hardware transactional memory systems are classified into the following three categories: how to perform version management and conflict detection, whether to support unbounded transactional memory and whether to support transactions nesting. Finally, we discussed two active research challenges: the relationship between transactional memory and Input/Output operations and Instruction Set Architecture (ISA) supporting.
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How to cite this article:

X. Wang, Zhenzhou Ji, Chen Fu and Mingzeng Hu, 2009. A Review of Hardware Transactional Memory in Multicore Processors. Information Technology Journal, 8: 965-970.

DOI: 10.3923/itj.2009.965.970

URL: https://scialert.net/abstract/?doi=itj.2009.965.970

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