Shen-Li Chen
Department of Electronic Engineering, National United University, MiaoLi City 36003, Taiwan
Min-Hua Lee
Department of Electronic Engineering, National United University, MiaoLi City 36003, Taiwan
ABSTRACT
Usually an MOST of I/O cells in integrated circuits will be in the form of multi-finger type. However, the non-uniform turned-on phenomenon in an MOST is deeply affecting the ESD reliability robustness. Here, the impacts of substrate pick-up stripe variation and a pWell structure adding are investigated in this stduy. ESD performance of these nMOSTs fabricated by a 0.35-μm CMOS process is evaluated in this work. Nevertheless it is desirous to improve the ESD capability of ESD elements. After a systematic analysis it is found that no matter what kind of channel length of nMOSTs, the P+ pick-up structure of source side and p-well structure in the 0.35-μm LV process are poor contributors to It2 robustness of elements, i.e., the substrate pick-up/ p-well structures will obviously lower the It2 level. Therefore, the source ends should avoid adding any P+ pick-up stripe and any p-well structure in the 0.35-μm process for communication systems.
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How to cite this article
Shen-Li Chen and Min-Hua Lee, 2013. Reliability Influences of Substrate Pick-up and Well Engineering of LV Nmosts
in Communication Modules. Information Technology Journal, 12: 7331-7335.
DOI: 10.3923/itj.2013.7331.7335
URL: https://scialert.net/abstract/?doi=itj.2013.7331.7335
DOI: 10.3923/itj.2013.7331.7335
URL: https://scialert.net/abstract/?doi=itj.2013.7331.7335
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