Asraf Mohamed Moubark
Department of Electrical, Electronic and System, Faculty of Engineering and Built Environment, University Kebangsaan Malaysia (UKM), 43600 Bangi, Selangor, Malaysia
Mohd Alauddin Mohd Ali
Department of Electrical, Electronic and System, Faculty of Engineering and Built Environment, University Kebangsaan Malaysia (UKM), 43600 Bangi, Selangor, Malaysia
Hilmi Sanusi
Department of Electrical, Electronic and System, Faculty of Engineering and Built Environment, University Kebangsaan Malaysia (UKM), 43600 Bangi, Selangor, Malaysia
Sawal Md. Ali
Department of Electrical, Electronic and System, Faculty of Engineering and Built Environment, University Kebangsaan Malaysia (UKM), 43600 Bangi, Selangor, Malaysia
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How to cite this article
Asraf Mohamed Moubark, Mohd Alauddin Mohd Ali, Hilmi Sanusi and Sawal Md. Ali, 2013. FPGA Implementation of Low Power Digital QPSK Modulator Using Verilog HDL. Journal of Applied Sciences, 13: 385-392.
DOI: 10.3923/jas.2013.385.392
URL: https://scialert.net/abstract/?doi=jas.2013.385.392
DOI: 10.3923/jas.2013.385.392
URL: https://scialert.net/abstract/?doi=jas.2013.385.392
anitha Reply
I read the paper, I need a help for DDS to generate sine & cosine i am doing the project, So i need to generate sine and cosine what you implemented in your paper. I need your guideline to write verilog code for dds to generate sine and cosine.