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Journal of Applied Sciences
  Year: 2009 | Volume: 9 | Issue: 2 | Page No.: 392-396
DOI: 10.3923/jas.2009.392.396
Leakage Tolerant, Noise Immune Domino Logic for Circuit Design in the Ultra Deep Submicron CMOS Technology for High Fan-in Gates
A. Peiravi, F. Moradi and Dag T. Wisland

Abstract:
In this study, the results of research carried out in order to develop and present a new logic for the design and development of leakage-tolerant and noise immune circuits in the ultra deep submicron CMOS technology are presented. We present novel domino logic to overcome the increasing static power consumption due to leakage power and to improve noise-immunity for high fan-in gates and compare it with standard domino logic. A noise metric and ISO-delay conditions are used to compare present proposed logic with conventional domino logic for various high fan-in OR gates. The results show remarkable improvement in noise immunity while drastically reducing power consumption.
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How to cite this article:

A. Peiravi, F. Moradi and Dag T. Wisland, 2009. Leakage Tolerant, Noise Immune Domino Logic for Circuit Design in the Ultra Deep Submicron CMOS Technology for High Fan-in Gates. Journal of Applied Sciences, 9: 392-396.

DOI: 10.3923/jas.2009.392.396

URL: http://scialert.net/abstract/?doi=jas.2009.392.396

 
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