It is proposed that the power supply of key circuit
modules could be gated to achieve significant reductions of leakage current,
with minimal costs to circuit speed and die area in 0.25, 0.18 and 0.07
μm technologies. This study describes an extension to power supply
gating using body overdrive and gate underdrive, analysis techniques to
predict leakage current and performance parameters, a procedure for optimization
of the sleep transistor size and simulation results that demonstrate the
accuracy of the analysis and advantages of the approach. A leakage current
estimation technique has been studied using the Berkeley Predictive Technology
Model Parameters. An estimation technique has been verified using ISCAS85
combinational Benchmark test circuits. Finally the optimization algorithm
has been verified using these same benchmark test circuits.
Ahmet Kucukkomurler and Steven L. Garverick, 2007. Sleep Transistor Sizing According to Circuit Speed, Silicon Area
and Leakage Current in High-Performance Digital Circuit Modules. Journal of Applied Sciences, 7: 958-964.